Applies to all electrical engineers who have/had lab in their BE and-or masters courses
Being an indian and a RVite at that, I had never imagined that labs will be tough to complete. All we had to do in BE was to copy a senior's ckt , rig up the ckt, tune the pots and get something which looked like what the senior had got. This is how we all passed the lab and assigned marks similar to the senior's record we were using.
It is not the way in MS!! Every univ has lot of funds to get all sorts of liscenced softwares to help (??) students. So every assignment goes like this
Day 1. Prof gives specs and deadline of 4 weeks...Everybody thinks 4 weeks is too long
1st week: Read some books/paper which use the words given in the specs
2nd week: Try completing the assignments of other courses
3rd week: Start with the design, not able to meet the specs, Panic!!!!!!!!
4th week: start consulting the prof, ask for extension. Prof agrees for 1 week extension
5th week: Assuming the design is right, start simulations, no luck
2 days before neew deadline: do night out, somehow get the simulation working
1day before: Do night out, connect on the breadboard, no output!! Panic!!!!
Day of submission, Panic!!, write report, work on the breadboard, Panic!!, submit the report without output
After 1 week: Prof gives his solution and says all designs that were used are wrong. Everybody gets a B
Panic!! think about improving the grade in next test atleast which is due 4 weeks from now
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3 comments:
LOL! couldnt have said it better...
well, there are exceptions..one is my FPGA project. ok, deadline is 4 weeks itself, but he also gives a soft deadline of 2 weeks and nobody wud hav done anything by then. then slogging starts and everybody manage to finish..not much design problems as codes are available online (;)) and ppl get an A if u get the lights flashing on the board (thats what my prof says), otherwise B+ or B..
u r lucky then!!!!
Here the prof checks for similarities in reports and gives a direct F if it is not original work!!
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